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/S2_L3A_WASP/files/32/U/QD/2022/SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2/
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Parent directory/--
DATA/-2022-10-18 07:00:15
MASKS/-2022-10-18 07:00:16
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B11.tif57.1 MiB2022-10-18 07:00:34
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B12.tif55.8 MiB2022-10-18 07:00:35
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B2.tif184.4 MiB2022-10-18 07:00:19
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B3.tif198.6 MiB2022-10-18 07:00:22
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B4.tif198.6 MiB2022-10-18 07:00:25
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B5.tif54.4 MiB2022-10-18 07:00:30
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B6.tif58.0 MiB2022-10-18 07:00:31
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B7.tif59.0 MiB2022-10-18 07:00:32
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B8.tif232.6 MiB2022-10-18 07:00:29
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_FRC_B8A.tif59.3 MiB2022-10-18 07:00:33
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_MTD_ALL.xml26.7 KiB2022-10-18 07:00:35
SENTINEL2X_20220915-000000-000_L3A_T32UQD_C_V1-2_QKL_ALL.jpg387.4 KiB2022-10-18 07:00:35