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/S2_L3A_WASP/files/32/U/PF/2024/SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2/
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DATA/-2024-08-11 22:02:52
MASKS/-2024-08-11 22:02:53
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B11.tif37.6 MiB2024-08-11 22:03:00
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B12.tif36.7 MiB2024-08-11 22:03:01
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B2.tif154.6 MiB2024-08-11 22:02:55
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B3.tif157.1 MiB2024-08-11 22:02:56
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B4.tif152.4 MiB2024-08-11 22:02:57
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B5.tif39.4 MiB2024-08-11 22:02:59
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B6.tif40.2 MiB2024-08-11 22:02:59
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B7.tif40.8 MiB2024-08-11 22:03:00
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B8.tif156.5 MiB2024-08-11 22:02:58
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_FRC_B8A.tif40.7 MiB2024-08-11 22:03:00
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_MTD_ALL.xml39.3 KiB2024-08-11 22:03:01
SENTINEL2X_20240715-000000-000_L3A_T32UPF_C_V1-2_QKL_ALL.jpg200.9 KiB2024-08-11 22:03:01