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/S2_L3A_WASP/files/32/U/PC/2022/SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2/
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DATA/-2023-01-10 16:37:47
MASKS/-2023-01-10 16:37:48
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B11.tif53.4 MiB2023-01-10 16:38:07
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B12.tif52.1 MiB2023-01-10 16:38:08
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B2.tif196.6 MiB2023-01-10 16:37:51
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B3.tif207.1 MiB2023-01-10 16:37:55
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B4.tif207.8 MiB2023-01-10 16:37:58
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B5.tif57.3 MiB2023-01-10 16:38:03
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B6.tif60.0 MiB2023-01-10 16:38:04
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B7.tif60.4 MiB2023-01-10 16:38:05
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B8.tif235.7 MiB2023-01-10 16:38:02
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_FRC_B8A.tif60.8 MiB2023-01-10 16:38:06
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_MTD_ALL.xml18.3 KiB2023-01-10 16:38:08
SENTINEL2X_20221215-000000-000_L3A_T32UPC_C_V1-2_QKL_ALL.jpg546.5 KiB2023-01-10 16:38:08