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/S2_L3A_WASP/files/32/U/MG/2024/SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2/
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DATA/-2024-06-13 07:13:53
MASKS/-2024-06-13 07:13:54
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B11.tif39.5 MiB2024-06-13 07:14:00
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B12.tif39.1 MiB2024-06-13 07:14:00
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B2.tif158.1 MiB2024-06-13 07:13:55
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B3.tif159.6 MiB2024-06-13 07:13:56
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B4.tif161.2 MiB2024-06-13 07:13:57
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B5.tif40.5 MiB2024-06-13 07:13:59
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B6.tif42.7 MiB2024-06-13 07:13:59
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B7.tif43.2 MiB2024-06-13 07:14:00
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B8.tif171.4 MiB2024-06-13 07:13:59
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_FRC_B8A.tif43.2 MiB2024-06-13 07:14:00
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_MTD_ALL.xml35.1 KiB2024-06-13 07:14:00
SENTINEL2X_20240515-000000-000_L3A_T32UMG_C_V1-2_QKL_ALL.jpg198.1 KiB2024-06-13 07:14:00