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/S2_L3A_WASP/files/32/U/MG/2024/SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2/
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DATA/-2024-02-09 22:22:10
MASKS/-2024-02-09 22:22:11
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B11.tif40.0 MiB2024-02-09 22:22:19
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B12.tif39.5 MiB2024-02-09 22:22:20
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B2.tif194.1 MiB2024-02-09 22:22:13
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B3.tif196.1 MiB2024-02-09 22:22:14
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B4.tif194.6 MiB2024-02-09 22:22:16
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B5.tif50.3 MiB2024-02-09 22:22:18
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B6.tif49.9 MiB2024-02-09 22:22:18
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B7.tif49.6 MiB2024-02-09 22:22:19
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B8.tif191.2 MiB2024-02-09 22:22:17
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_FRC_B8A.tif48.2 MiB2024-02-09 22:22:19
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_MTD_ALL.xml26.7 KiB2024-02-09 22:22:20
SENTINEL2X_20240115-000000-000_L3A_T32UMG_C_V1-2_QKL_ALL.jpg276.1 KiB2024-02-09 22:22:20