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/S2_L3A_WASP/files/32/U/MF/2024/SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2/
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DATA/-2024-09-09 07:05:27
MASKS/-2024-09-09 07:05:28
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B11.tif32.7 MiB2024-09-09 07:05:34
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B12.tif31.7 MiB2024-09-09 07:05:34
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B2.tif150.3 MiB2024-09-09 07:05:29
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B3.tif150.4 MiB2024-09-09 07:05:30
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B4.tif142.4 MiB2024-09-09 07:05:31
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B5.tif35.9 MiB2024-09-09 07:05:33
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B6.tif36.1 MiB2024-09-09 07:05:33
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B7.tif36.6 MiB2024-09-09 07:05:33
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B8.tif138.7 MiB2024-09-09 07:05:33
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_FRC_B8A.tif36.3 MiB2024-09-09 07:05:34
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_MTD_ALL.xml42.1 KiB2024-09-09 07:05:34
SENTINEL2X_20240815-000000-000_L3A_T32UMF_C_V1-2_QKL_ALL.jpg155.2 KiB2024-09-09 07:05:34