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/S2_L3A_WASP/files/32/U/MF/2024/SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2/
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DATA/-2024-06-13 07:34:12
MASKS/-2024-06-13 07:34:12
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B11.tif35.1 MiB2024-06-13 07:34:19
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B12.tif34.4 MiB2024-06-13 07:34:19
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B2.tif147.2 MiB2024-06-13 07:34:14
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B3.tif147.2 MiB2024-06-13 07:34:15
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B4.tif147.5 MiB2024-06-13 07:34:16
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B5.tif37.1 MiB2024-06-13 07:34:18
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B6.tif38.4 MiB2024-06-13 07:34:18
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B7.tif38.9 MiB2024-06-13 07:34:18
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B8.tif153.0 MiB2024-06-13 07:34:17
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_FRC_B8A.tif38.9 MiB2024-06-13 07:34:19
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_MTD_ALL.xml37.9 KiB2024-06-13 07:34:19
SENTINEL2X_20240515-000000-000_L3A_T32UMF_C_V1-2_QKL_ALL.jpg158.4 KiB2024-06-13 07:34:19