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/S2_L3A_WASP/files/32/U/MF/2023/SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2/
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DATA/-2023-10-13 22:22:43
MASKS/-2023-10-13 22:22:44
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B11.tif33.0 MiB2023-10-13 22:22:58
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B12.tif32.6 MiB2023-10-13 22:22:58
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B2.tif155.1 MiB2023-10-13 22:22:47
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B3.tif154.4 MiB2023-10-13 22:22:49
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B4.tif150.5 MiB2023-10-13 22:22:52
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B5.tif38.8 MiB2023-10-13 22:22:55
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B6.tif39.1 MiB2023-10-13 22:22:56
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B7.tif39.6 MiB2023-10-13 22:22:56
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B8.tif146.7 MiB2023-10-13 22:22:54
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_FRC_B8A.tif38.6 MiB2023-10-13 22:22:57
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_MTD_ALL.xml32.3 KiB2023-10-13 22:22:58
SENTINEL2X_20230915-000000-000_L3A_T32UMF_C_V1-2_QKL_ALL.jpg174.0 KiB2023-10-13 22:22:58