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/S2_L3A_WASP/files/32/U/MF/2022/SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2/
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DATA/-2022-10-18 08:32:28
MASKS/-2022-10-18 08:32:30
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B11.tif36.9 MiB2022-10-18 08:32:44
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B12.tif36.5 MiB2022-10-18 08:32:45
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B2.tif157.4 MiB2022-10-18 08:32:33
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B3.tif157.7 MiB2022-10-18 08:32:35
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B4.tif154.9 MiB2022-10-18 08:32:38
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B5.tif40.0 MiB2022-10-18 08:32:41
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B6.tif40.5 MiB2022-10-18 08:32:42
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B7.tif40.9 MiB2022-10-18 08:32:43
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B8.tif155.0 MiB2022-10-18 08:32:41
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_FRC_B8A.tif40.6 MiB2022-10-18 08:32:43
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_MTD_ALL.xml37.9 KiB2022-10-18 08:32:45
SENTINEL2X_20220915-000000-000_L3A_T32UMF_C_V1-2_QKL_ALL.jpg183.4 KiB2022-10-18 08:32:45