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/S2_L3A_WASP/files/32/U/MD/2024/SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2/
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DATA/-2024-04-29 13:50:28
MASKS/-2024-04-29 13:50:29
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B11.tif58.0 MiB2024-04-29 13:50:38
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B12.tif56.7 MiB2024-04-29 13:50:38
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B2.tif195.1 MiB2024-04-29 13:50:30
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B3.tif205.2 MiB2024-04-29 13:50:32
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B4.tif210.8 MiB2024-04-29 13:50:33
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B5.tif55.8 MiB2024-04-29 13:50:36
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B6.tif60.0 MiB2024-04-29 13:50:36
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B7.tif60.8 MiB2024-04-29 13:50:37
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B8.tif238.4 MiB2024-04-29 13:50:35
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_FRC_B8A.tif61.0 MiB2024-04-29 13:50:37
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_MTD_ALL.xml16.9 KiB2024-04-29 13:50:38
SENTINEL2X_20240315-000000-000_L3A_T32UMD_C_V1-2_QKL_ALL.jpg380.1 KiB2024-04-29 13:50:38