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/S2_L3A_WASP/files/32/U/MD/2022/SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2/
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DATA/-2022-05-10 06:00:22
MASKS/-2022-05-10 06:00:24
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B11.tif58.1 MiB2022-05-10 06:00:50
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B12.tif57.9 MiB2022-05-10 06:00:51
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B2.tif195.6 MiB2022-05-10 06:00:28
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B3.tif204.4 MiB2022-05-10 06:00:33
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B4.tif212.2 MiB2022-05-10 06:00:38
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B5.tif55.9 MiB2022-05-10 06:00:44
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B6.tif59.7 MiB2022-05-10 06:00:45
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B7.tif60.9 MiB2022-05-10 06:00:47
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B8.tif237.2 MiB2022-05-10 06:00:43
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_FRC_B8A.tif61.2 MiB2022-05-10 06:00:48
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_MTD_ALL.xml23.9 KiB2022-05-10 06:00:51
SENTINEL2X_20220415-000000-000_L3A_T32UMD_C_V1-2_QKL_ALL.jpg448.7 KiB2022-05-10 06:00:51