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/S2_L3A_WASP/files/32/U/MC/2024/SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2/
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DATA/-2024-10-15 23:51:38
MASKS/-2024-10-15 23:51:40
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B11.tif58.1 MiB2024-10-15 23:51:50
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B12.tif56.8 MiB2024-10-15 23:51:51
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B2.tif190.2 MiB2024-10-15 23:51:41
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B3.tif208.2 MiB2024-10-15 23:51:43
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B4.tif199.4 MiB2024-10-15 23:51:45
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B5.tif56.6 MiB2024-10-15 23:51:48
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B6.tif60.7 MiB2024-10-15 23:51:48
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B7.tif61.9 MiB2024-10-15 23:51:49
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B8.tif244.0 MiB2024-10-15 23:51:47
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_FRC_B8A.tif62.2 MiB2024-10-15 23:51:49
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_MTD_ALL.xml30.9 KiB2024-10-15 23:51:51
SENTINEL2X_20240915-000000-000_L3A_T32UMC_C_V1-2_QKL_ALL.jpg465.8 KiB2024-10-15 23:51:51