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/S2_L3A_WASP/files/32/U/MC/2024/SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2/
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DATA/-2024-03-10 23:58:57
MASKS/-2024-03-10 23:58:57
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B11.tif55.6 MiB2024-03-10 23:59:07
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B12.tif53.8 MiB2024-03-10 23:59:08
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B2.tif193.8 MiB2024-03-10 23:58:59
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B3.tif200.8 MiB2024-03-10 23:59:01
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B4.tif206.4 MiB2024-03-10 23:59:03
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B5.tif54.3 MiB2024-03-10 23:59:05
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B6.tif57.3 MiB2024-03-10 23:59:06
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B7.tif58.0 MiB2024-03-10 23:59:06
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B8.tif228.2 MiB2024-03-10 23:59:05
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_FRC_B8A.tif58.4 MiB2024-03-10 23:59:07
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_MTD_ALL.xml15.5 KiB2024-03-10 23:59:08
SENTINEL2X_20240215-000000-000_L3A_T32UMC_C_V1-2_QKL_ALL.jpg402.7 KiB2024-03-10 23:59:08