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/S2_L3A_WASP/files/32/U/MC/2023/SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2/
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DATA/-2023-10-15 04:08:17
MASKS/-2023-10-15 04:08:18
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B11.tif58.0 MiB2023-10-15 04:08:38
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B12.tif57.0 MiB2023-10-15 04:08:39
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B2.tif195.8 MiB2023-10-15 04:08:22
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B3.tif207.8 MiB2023-10-15 04:08:25
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B4.tif208.4 MiB2023-10-15 04:08:29
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B5.tif56.3 MiB2023-10-15 04:08:34
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B6.tif60.2 MiB2023-10-15 04:08:35
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B7.tif61.4 MiB2023-10-15 04:08:36
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B8.tif241.0 MiB2023-10-15 04:08:33
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_FRC_B8A.tif61.7 MiB2023-10-15 04:08:37
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_MTD_ALL.xml26.7 KiB2023-10-15 04:08:39
SENTINEL2X_20230915-000000-000_L3A_T32UMC_C_V1-2_QKL_ALL.jpg470.1 KiB2023-10-15 04:08:39