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/S2_L3A_WASP/files/32/U/MC/2022/SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2/
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DATA/-2022-10-18 05:20:04
MASKS/-2022-10-18 05:20:06
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B11.tif58.6 MiB2022-10-18 05:20:26
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B12.tif57.5 MiB2022-10-18 05:20:27
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B2.tif202.4 MiB2022-10-18 05:20:09
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B3.tif211.0 MiB2022-10-18 05:20:13
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B4.tif215.9 MiB2022-10-18 05:20:17
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B5.tif56.7 MiB2022-10-18 05:20:22
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B6.tif59.4 MiB2022-10-18 05:20:23
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B7.tif60.5 MiB2022-10-18 05:20:24
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B8.tif239.3 MiB2022-10-18 05:20:21
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_FRC_B8A.tif60.8 MiB2022-10-18 05:20:25
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_MTD_ALL.xml23.9 KiB2022-10-18 05:20:27
SENTINEL2X_20220915-000000-000_L3A_T32UMC_C_V1-2_QKL_ALL.jpg490.2 KiB2022-10-18 05:20:27