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/S2_L3A_WASP/files/32/U/MC/2021/SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2/
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DATA/-2021-06-01 10:11:30
MASKS/-2021-06-01 10:11:36
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B11.tif57.3 MiB2021-06-01 10:12:05
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B12.tif56.2 MiB2021-06-01 10:12:06
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B2.tif201.2 MiB2021-06-01 10:11:41
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B3.tif208.0 MiB2021-06-01 10:11:46
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B4.tif215.1 MiB2021-06-01 10:11:51
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B5.tif55.9 MiB2021-06-01 10:11:59
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B6.tif59.7 MiB2021-06-01 10:12:00
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B7.tif60.5 MiB2021-06-01 10:12:01
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B8.tif236.8 MiB2021-06-01 10:11:57
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_FRC_B8A.tif60.7 MiB2021-06-01 10:12:03
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_MTD_ALL.xml18.3 KiB2021-06-01 10:12:07
SENTINEL2X_20210315-000000-000_L3A_T32UMC_C_V1-2_QKL_ALL.jpg408.2 KiB2021-06-01 10:12:07