| Parent directory/ | - | - |
| DATA/ | - | 2022-06-12 04:13:11 |
| MASKS/ | - | 2022-06-12 04:13:14 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B11.tif | 57.3 MiB | 2022-06-12 04:13:38 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B12.tif | 55.9 MiB | 2022-06-12 04:13:40 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B2.tif | 188.6 MiB | 2022-06-12 04:13:18 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B3.tif | 206.6 MiB | 2022-06-12 04:13:22 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B4.tif | 204.1 MiB | 2022-06-12 04:13:27 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B5.tif | 55.6 MiB | 2022-06-12 04:13:33 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B6.tif | 59.5 MiB | 2022-06-12 04:13:34 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B7.tif | 60.9 MiB | 2022-06-12 04:13:36 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B8.tif | 240.5 MiB | 2022-06-12 04:13:32 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_FRC_B8A.tif | 61.1 MiB | 2022-06-12 04:13:37 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_MTD_ALL.xml | 22.5 KiB | 2022-06-12 04:13:40 |
| SENTINEL2X_20220515-000000-000_L3A_T32ULV_C_V1-2_QKL_ALL.jpg | 425.7 KiB | 2022-06-12 04:13:40 |