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/S2_L3A_WASP/files/32/U/LD/2022/SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2/
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DATA/-2022-10-18 08:48:42
MASKS/-2022-10-18 08:48:44
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B11.tif58.0 MiB2022-10-18 08:49:03
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B12.tif56.9 MiB2022-10-18 08:49:04
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B2.tif194.8 MiB2022-10-18 08:48:47
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B3.tif203.3 MiB2022-10-18 08:48:51
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B4.tif209.5 MiB2022-10-18 08:48:54
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B5.tif55.3 MiB2022-10-18 08:48:59
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B6.tif59.2 MiB2022-10-18 08:49:00
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B7.tif60.4 MiB2022-10-18 08:49:01
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B8.tif238.3 MiB2022-10-18 08:48:58
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_FRC_B8A.tif60.6 MiB2022-10-18 08:49:02
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_MTD_ALL.xml33.7 KiB2022-10-18 08:49:04
SENTINEL2X_20220915-000000-000_L3A_T32ULD_C_V1-2_QKL_ALL.jpg386.9 KiB2022-10-18 08:49:04